A data transceiver architecture using serializer/deserializer (SERDES) often employs phase interpolators or similar functional circuits to offset a transmit (or receive) frequency relative to a local timing reference so that the SERDES can transmit (or receive) data at the same frequency as a frequency of data transmitted (or received) from its far-end peer device as detected by a SERDES receiver (or transmitter).
Phase interpolators (PIs) are devices that can input a clock and shift its phase according to an analog or digital command. A PI can be used to achieve a TX (or RX) frequency that is different from a frequency of a phase locked loop (PLL) or a frequency of a PLL multiple. Improvements in such PI-based data receiving/transmitting methods remain desired.
The details of various embodiments of the methods and systems are set forth in the accompanying drawings and the description below.